Currently, I research error detection mechanisms at thread and hardware module level in hybrid reconfigurable systems. My vision is that future reconfigurable computer systems will put use to unused silicon space by dynamically duplicating threads/ hardware modules, comparing their results and signatures and thus implementing continuous reliability monitoring. Once an unreliable thread or hardware module is identified, the computing system may react in several ways: reconfiguring the thread or hardware module, moving it to another location on the reconfigurable device or switching its modality from hardware to software. My ultimate research goal is to increase the reliability of reconfigurable hybrid computer systems and to prolong their lifetime.
I have additional interests in hardware design, processor and on-chip communication architectures.