Mapping LogicNets to FPGA
Project (Systementwurf-Teamprojekt) in the Winter Semester 2026/2027
Background: LogicNets [1] is a type of a Deep Neural Network (DNN) that uses the Lookup-Tables (LUT) in a Field-Programmable Gate Array (FPGA) as building block for implementing the neurons of a DNN. All parameters and computations of a neuron, including weights and bias, multiply & accumulates and the non-linear activation function are converted into a truth table representation and are then directly mapped to the LUTs of an FPGA. Without multipliers, adders, and weight memories the DNN inference step becomes extremely fast. Hence, LogicNets-DNNs not only exhibit very high throughput but also ultra-low latency compared to CPUs or GPUs. This is of interest for latency-senstitive applications in industrial automation, trigger detection in particle physics, etc.
The challenge for LogicNets DNNs is that the size of LUTs grows exponentially with their number of inputs. Even with quantization of weights and activations down to a few bits, the DNN circuits quickly exceed the logic capacity of FPGAs. Our recent research addresses this challenge by compressing (approximating) LogicNets DNNs at two levels: reducing the precision and connectivity of the network during training and by approximating individual neurons at the register-transfer level (RTL), e.g., with a method called Boolean matrix factorization. We have developed CLAS [2], a toolflow that given a dataset performs these approximations and creates a number of LogicNets DNN circuits in Verilog which differ in accuracy and resource requirements and form trade-offs. So far, these circuits have only been evaluated in simulation.
Goal and Tasks: This project should develop a demonstrator to bridge the missing step from simulation of Verilog to a running FPGA implementation. This allows us to study approximated LogicNets in practice. As a test case, handwritten-digit recognition (MNIST dataset, downscaled to 8×8 pixels) will be used. MNIST is a standard benchmark for such DNNs that is also practical to demonstrate live. The project will cover the following four main tasks:
Getting started: run the CLAS toolflow on a provided LogicNet network (+ dataset) and understand its stages.
Interface development: add an input/output interface (e.g., UART or on-chip ARM processor) for the generated LogicNets DNN, implement it on an FPGA (e.g., Xilinx ZCU104 board), and check that the physical FPGA implementation reproduces the simulation results.
Evaluation: create several LogicNets DNNs trained on the MNIST dataset and own, self-drawn digits, synthesize them to the FPGA, measure accuracy, LUT usage, and speed, and compare these metrics with the estimates from simulation.
Graphical interface: develop a dashboard that allows the user to select a LogicNets circuit and automatically build, load and test its FPGA implementation, plus a live mode where the FPGA board classifies digits drawn on the PC.
All group members start together with task 1. Then, the group organizes itself into sub-teams based on clearly defined interfaces between different tasks and sub-tasks. The integration of the results into the final demonstrator will again be done by the whole group.
Prerequisites: You should bring a fundamental understanding of digital design, solid Python programming skills, and basic knowledge of a hardware description language such as VHDL or Verlog. A background in machine learning is helpful but not required.
What you will learn: In this project, you will build up skills in the following areas:
- Deep neural networks, in particular LogicNets, a recent research idea for ultra-low latency and high throughput DNNs
- Working with FPGA boards and FPGA synthesis tools
- Model compression techniques: quantization, pruning, approximation at the circuit level
- Creating a hardware-software co-designed demonstrator with a PC and an FPGA platform
- Soft skills, organizing and working in a team
[1] Umuroglu, Yaman, Yash Akhauri, Nicholas James Fraser, and Michaela Blott. "LogicNets: Co-designed neural networks and circuits for extreme-throughput applications." In 2020 30th International Conference on Field-Programmable Logic and Applications (FPL), pp. 291-297. IEEE, 2020.
[2] Jafari, Atousa, Amir Hossein Hadipour, Muhammad Awais, Mohammadparsa Rostamzadehkhameneh, Hassan Ghasemzadeh Mohammadi, and Marco Platzner. "CLAS: A Cross-Layer Approximate Synthesis Framework for LUT-Based DNN Accelerators." In International Symposium on Applied Reconfigurable Computing, pp. 255-272. Cham: Springer Nature Switzerland, 2026.
