Available Topics
- Bring your own idea! (BA/MA, Marco Platzner)
- Implementation and Evaluation of Deep Differentiable Logic Gate Networks on FPGA (MA, Atousa Jafari)
- Hardware Trojans in Custom-tailored Dataflow Accelerators (MA, Qazi Arbab Ahmed)
- Implementation of a Performant and Easy-to-use Memory Interface for Recon(R)OS (MA, Alexander Nowosad)
- Survey of ROS FPGA Frameworks (MA, Alexander Nowosad)
- Accurate Quality Estimation of Approximate Accelerators via Advanced ML Methods (MA, Muhammad Awais)
- Clustering of Approximate Library Components for Efficient Search-based Synthesis (MA, Muhammad Awais)
Are you interested but have questions about details? Feel free to write an email to the supervisor. If you have a coarse idea about a topic you would like to work on, please contact us. Concrete topics often emerge from discussions.
In the above list, BA stands for Bachelor Thesis and MA for Master Thesis. Sometimes, a topic can be designed either as a Bachelor Thesis or a Master Thesis. Unless noted otherwise in the announcement, you can decide for yourself if you want to write your thesis in English or German.
Running Theses
- Design and Integration of Intra-Process Communication for ROS 2 into ReconROS (MA, Alexander Nowosad)
- Hybrid approximation of DNNs using LogicNets (MA, Muhammad Awais)
Completed Theses
Exploring Custom FPGA Accelerators for DNN-based RF Fingerprinting
L.-S. Henke, Exploring Custom FPGA Accelerators for DNN-Based RF Fingerprinting, 2024.
Controlling I/O Devices from Hardware-Mapped ReconROS Nodes
M. Hartinger, Controlling I/O Devices from Hardware-Mapped ReconROS Nodes, Paderborn University, 2024.
Efficient Neural Network Inference for Velocity Estimation in Athletic Relay Races on a Microcontroller
D.B. Anantha Rao, Efficient Neural Network Inference for Velocity Estimation in Athletic Relay Races on a Microcontroller, Paderborn University, 2023.
An Evaluation of XCS on the OpenAI Gym
F. Mehlich, An Evaluation of XCS on the OpenAI Gym, Paderborn University, Paderborn, 2023.
A Comparison of Algorithms for the Generation of Layouts based on Reconfigurable Slots on FPGAs
Y. Tadakamalla, A Comparison of Algorithms for the Generation of Layouts Based on Reconfigurable Slots on FPGAs, Paderborn University, 2023.
Design and Realization of Optimized Intra-FPGA ROS 2 Communication
S.H. Middeke, Design and Realization of Optimized Intra-FPGA ROS 2 Communication, Paderborn University, 2023.
A Hardware/Software Co-designed ORB-SLAM2 Algorithm for FPGA
S. Thiele, A Hardware/Software Co-Designed ORB-SLAM2 Algorithm for FPGA, Paderborn University, 2023.
Implementation and Evaluation of a ReconROS-based Obstacle Avoidance Architecture for Autonomous Robots
A. Abooof, Implementation and Evaluation of a ReconROS-Based Obstacle Avoidance Architecture for Autonomous Robots, Paderborn University, 2023.
Multithreaded Software/Hardware Programming with ReconOS/Zephyr on a RISC-V-based System-on-Chip
A.P. Rao, Multithreaded Software/Hardware Programming with ReconOS/Zephyr on a RISC-V-Based System-on-Chip, Paderborn University, 2023.
Effizienzanalyse leichtgewichtiger Neuronaler Netze für FPGA-basierte Modulationsklassifikation
F. Simon-Mertens, Effizienzanalyse leichtgewichtiger Neuronaler Netze für FPGA-basierte Modulationsklassifikation, Paderborn University, 2023.
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